This invention relates to a semiconductor device, in particular, to a semiconductor device having pads connected to package terminals (or pins) arranged along a center line on a surface of a semiconductor chip.
Recently, improvements in processing or response speed and enlargement of capacity of the semiconductor device are advanced. Moreover, miniaturization of a package is advanced to miniaturize the semiconductor device. A memory device having gigabit memory capacity and mounted on a small sized package has been developed as a dynamic random access memory (hereinafter simply called DRAM). A ball grid array (hereinafter simply called BGA) is known as the small sized package. The BGA having solder balls arranged on a package substrate is a surface mounting type. The BGA is adopted for a general-purpose DRAM, such as a DDR3 DRAM.
In the general-purpose DRAM, pin arrangement (i.e. assignment of signals to solder balls) is standardized by Joint Electron Device Engineering Council (JEDEC) and employed by DRAM vendors in common. Furthermore, there is a case where a 4-bit structure device (or a ×4 device) or an 8-bit structure device (or a ×8 device) is manufactured by the use of the same semiconductor chip as a 16-bit structure device (or a ×16-bit device). That is, there is a semiconductor chip to which a bonding option or a fuse option is provided to serve as any one of the ×4, the ×8 and the ×16 device.
The ×4 and the ×8 devices do not have pins called DQ system high-order bit side pins in the ×16 device. Accordingly, DQ system pins of the ×4 or ×8 device are connected to pads called DQ system low-order bit side pads with connecting wires in a related semiconductor device. As a result, the related semiconductor device has problems that the connecting wires connected to the DQ system pins of the ×4 or ×8 device are long and have high wiring density. Therefore, it is hard to secure enough wiring width and wiring space.